The present invention relates to a Josephson memory and, more particularly, to a buffered, nondestructive-readout Josephson memory using a minimal number of gates.
Most of the existing Josephson memories have a "half-select" problem, and their operating margins and hence the yield are low. The half-select problem arises from the fact that a cell in a memory array, organized as a matrix of rows and columns, is selected by coincidentally applying currents in a row and a column. While the selected memory cell senses two units of current, all of the other nonselected cells in that particular row and column still sense one unit of current and thereby become "half-selected". The maximum theoretical margin for a cell with the half-selected condition is limited to +/-33% since the cell has to discriminate between one and two units of current. In reality, the margin is even smaller because the Josephson memory gates are usually biased at about half of their electrical currents to enlarge the input operating window, and the dynamics of gates at low biased currents is not well controlled.
P. Wolf invented a basic Josephson cell which eliminates inherent set-up cycle problems of such cells and the difficulties associated with diagonal decoding of these memory cells, obtaining improvements in memory density. The basic Wolf cell operates by establishing or interrupting a circulating current in a superconducting storage loop to represent stored binary information, e.g. a binary "1" or "0". See P. Wolf, "Two-Junction Josephson Memory," IBM Technical Disclosure Bulletin, Volume 26, page 214, Jun. 1973.
W. H. Henkel and J. H. Greiner describe in their paper entitled "Experimental Flux Quantum NDRO Josephson Memory Cell," IEEE J. Solid-State Circuits, Volume SC-14, pages 794-796, 1979, a nondestructive readout (NDRO) memory with two gates, one for the write operation and one for sensing the data. To improve the reliability of the memory and the margins on the write signals, S. M. Faris teaches, in U.S. Pat. No. 4,151,605 (which issued in Apr. 1979), to use a buffer gate in front of the write gate to eliminate the aforementioned half-select problem. This increases the gate count per cell to three but enables a slightly smaller area per each memory cell. However, Faris' cell still has the half-select problem for the sense line. A fully buffered cell of the type described in the aforementioned article by Henkel et al. would require four gates per cell, namely an additional AND gate to buffer the sense gate.
The pressing quest to provide ever faster memories of high density, low power, using a minimal number of gates per cell and free of the half-select and similar problems has not been met by the prior art.